This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to prevent epitaxial growth in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continue to shrink, conventional semiconductor processing is increasingly challenged to make structures at finer dimensions. Planar field effect transistor (FET) technology has become constrained at smaller geometries due to leakage effects. The semiconductor industry has found an alternative approach to planar FETs with fin field effect transistors (FinFETs) to reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up from the surface of the semiconductor substrate upon which the FinFET is located. Due to the many superior attributes, especially in the areas of device performance, off-state leakage and foot print, FinFETs are replacing planar FETs, to enable the scaling of gate lengths to 14 nm and below. In addition, a type of FinFET called a multiple gate field-effect transistor, or MuGFET, is often used in logic devices.
A typical static random-access memory (static RAM or SRAM)), when implemented in FinFETs, is comprised of three different types of FinFETs: pull-up (PU) FinFETs, pass-gate (PG) FinFETs, and pull-down (PD) FinFETs. In dimensions of 14 nm and below, the pull up FinFET active distance is one of factors which limit the density of the integrated circuit. The PU FinFET to PU FinFET epitaxy short is an SRAM and logic device yield issue.